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1989-10-08
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ic locator. some tool which will take as input a list of components and a list
of the connections between them, and produce a component placement
scheme which minimizes the overall distance of the connections. doing
this could greatly reduce the amount of computing needed by the A*
algorithm.
future enhancements
lim 4.0 or virtual memory swapped out to disk
square screen aspect ratio
interactive drawing
incremental save after every connect
hole previewer without routing the board (use 0/1 for rat nester)
rectangles for exclusion from routing (bus cutouts)
gold fingers (filled in blocks)
output compression (enumeration for sparse)
electrically connected cells (treat source & dest as set)
fat traces for vcc & gnd
report on closeness to optimality
beep per connect and at end (activate by switch)
capacitors, resistors, diodes, sims, etc.
circuit simulation
keep track of input line number for error messages
surface mount
rat's nest, distinguish chips by colors (cycle through chips),
hilight traces to/from a chip, calculate 'gravity'
per chip (direction it wants to move, based on connections,
relative strength of pull)
more layers (not just front and back)
can i get more speed out of expanding SetQueue in-line in ReSetQueue?
(mouse-driven?) pcb editor with menu of cell types
allow horizontal-and-vertical only per side routing option
(high penalty per distance)
associate a name with holes, so they can be position-independent too
priority level, not just in order of occurrence
distinguish routing vias from original holes (by color)
panic-mode incest to reuse queue memory (from end of queue) when no
more memory is available
option to siphon output to a file while sending it to the screen too
take into account thickness of (1) board, and (2) hole donut